| Hardware Design Engineer 5 | Remote | C2C at Remote, Remote, USA |
| Email: [email protected] |
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http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=810793&uid= From: SAGAR TOMAR, IT TRAILBLAZERS LLC [email protected] Reply to: [email protected] Hardware Design Engineer 5 Location : Remote Type : C2C Sub-chip & full-chip level DFT Insertions which primarily include Scan, ATPG, MBIST and associated simulations. Retargeting block level test patterns to sub chip & full chip. Person needs to be an expert at Scan ATPG, Stuck-at, at-speed insertions, boundary coverage, compression & retargeting flows using Mentor Tessent EDA tool. Should have a good understanding of STA (Static Timing Analysis) & constraint generation. Independently be able to debug mismatches with very little help/guidance. Able to communicate clearly and work with other folks (esp. during initial ramp). Document results/progress and provide timely updates." Years of Experience Required 10+ years Degrees or certifications required experience is more important Disqualifiers Low tenure Large gap since working with the tools Best vs. Average Previous MSFT experience Person needs to be an expert at Scan ATPG, Stuck-at, at-speed insertions, boundary coverage, compression & retargeting flows using Mentor Tessent EDA tool. Should have a good understanding of STA (Static Timing Analysis) & constraint generation. Good written and verbal communication Performance Indicators Meeting deadlines 1. Scan ATPG 4-5 years 2. MBIST 4-5 years 3. GLS 4-5 years Sagar Tomar Technical Recruiter IT TRAIL BLAZERS LLC O : +1(732)-227-1772* 226 D : +1(848)-271-1272 ( Call or Text) Add me on LinkedIn : linkedin.com/in/sagar-t-95097a255 E : [email protected] Suite #306, 510 Thornall St, Edison NJ 08837 Keywords: information technology New Jersey http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=810793&uid= |
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| 12:16 AM 01-Nov-23 |