| ASIC Package Engineer at Atlanta ,GA at Atlanta, Georgia, USA |
| Email: [email protected] |
|
http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=2324173&uid= From: Dheeraj srivastava, Datum Software [email protected] Reply to: [email protected] Currently, we have an opening for ASIC Package Engineer SI/PI with our Client at San Jose, CA | On-Site . I appreciate your time and look forward to hearing from you. ASIC Package Engineer SI/PI 100% ONSITE ROLE San Jose, CA Responsibilities Drive chip-package-system co-design by driving signal and power integrity requirements analysis and optimization Define power tree structure, netlists, etc for High Performance Computing based on 2.5D/3D package technology Run pre-layout and post-layout simulation flow with a focus on high-speed interface and PDN, create simulation models and develop simulation methodology for SIPI. Develop SIPI validation methodology and develop detailed engineering test plans Validate high speed interface and PDN impedance in lab to correlate simulation results and improve design flow Work closely with Architecture, ASIC, Mixed Signal, Package, and PCB Design teams to design and ensure package/system SI/PI performance meets expectation before Gerber out, also work closely with Design Validation teams to support SI/PI failure analysis Package/Board power delivery network AC+DC simulation for low-voltage/high-current supplies. Development of next generation memory interface considering Input/Output Physical Layer (IO PHY), SI/PI and physical design. Preferred Qualifications: Bachelor or Master degree in Electrical Engineering, Physics, Mathematics, or related field (or equivalent experience) 5+ years of experience in SIPI simulation and validation areas Experience with high-speed interface protocols such as MIPI, PCIe, memory, HBM and USB. Experience using Cadecen Sigrity, PowerSI, Ansys SIwave, Keysight ADS, 3D layout and Ansys HFSS Experience with consumer hardware design, review and bring-up process, CAD tools, constraint manager etc. Solid understanding and experience in computational electromagnetics and transmission line theory. Drive chip-package-system co-design by driving signal and power integrity requirements analysis and optimization Define power tree structure, netlists, etc for High Performance Computing based on 2.5D/3D package technology Run pre-layout and post-layout simulation flow with a focus on high-speed interface and PDN, create simulation models and develop simulation methodology for SIPI. Develop SIPI validation methodology and develop detailed engineering test plans Validate high speed interface and PDN impedance in lab to correlate simulation results and improve design flow Work closely with Architecture, ASIC, Mixed Signal, Package, and PCB Design teams to design and ensure package/system SI/PI performance meets expectation before Gerber out, also work closely with Design Validation teams to support SI/PI failure analysis Package/Board power delivery network AC+DC simulation for low-voltage/high-current supplies. Development of next generation memory interface considering Input/Output Physical Layer (IO PHY), SI/PI and physical design Keywords: California Colorado ASIC Package Engineer at Atlanta ,GA [email protected] http://bit.ly/4ey8w48 https://jobs.nvoids.com/job_details.jsp?id=2324173&uid= |
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| 08:33 PM 08-Apr-25 |