| Digital Design Engineering RTL Design at Remote, Remote, USA |
| Email: [email protected] |
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https://jobs.nvoids.com/job_details.jsp?id=1696540&uid= From: Darshana Sakroo, LiveMindz [email protected] Reply to: [email protected] Digital Design Engineering / RTL Design Location: Sunnyvale, CA Full Time Only ( No H1B, OPT and CPT) Independent Visa Only Exp: 8 to 15 years Digital Design Engineering/RTL Design Services: ASIC design and integration familiar with lint/cdc/rdc challenges, comfortable with scripting. 1 engineer needs to be matlab-fluent (Must) Architecture and microarchitecture of System on a Chip (SOC) subsystems, Intellectual Property Functional Blocks (IPs), sub-IPs, modules, and library components Digital design, using System Verilog and/or Verilog RTL, RTL generators (in Python), and/or high-level synthesis (HLS). RTL integration of SoC subsystems, IPs, sub-IPs, modules, and library components SoC-level integration Support mapping of RTL on Zebu and HAPS for IP bring up and E2E validation Design for low power and power intent design using Unified Power Format (UPF) Constraint development, synthesis, timing closure, and optimization of the design Code quality checks, including but not limited to Linting, Clock Domain Crossing, Reset Domain Crossing Debug and bug fixes [email protected] / 469 965 0486 Keywords: California Digital Design Engineering RTL Design [email protected] https://jobs.nvoids.com/job_details.jsp?id=1696540&uid= |
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| 07:24 PM 27-Aug-24 |